The present invention relates to integrated circuits, generally, and more specifically to a buffer for interfacing a low-voltage technology with a relatively high-voltage technology.
Advances in the semiconductor arts have driven devices to decreasing sizes operating at increasing speeds. This continuous effort to maximize the performance of integrated circuits (xe2x80x9cICsxe2x80x9d) has produced several additional benefits, including decreased operating voltages and reductions in power consumption.
As MOS technology scales below 0.2 xcexcm, acceptable supply voltages have lowered below the previous 3.3V and 5V standards. As lower and lower operating voltage IC technology is developed and commercialized, however, a distinct problem has arisen. Mostly because of economic reasons, electronic systems often use ICs that span several technology generations, each generation having different supply voltage requirements. The ability to interface newer low power ICs with their predecessors where each IC has a different range of operating voltages is of concern, particularly as it relates to metal oxide semiconductors (xe2x80x9cMOSxe2x80x9d). Interfacing an older higher operating voltage IC with a lower operating voltage technology may cause reliability issues and/or temporary or even permanent damage. For example, the buffer circuits of a 1.5V IC can neither provide nor sustain (when in a high impedance state) a 3.3V drive.
To overcome this interface problem, several solutions have been proposed. One approach entails the development of MOS devices capable of handling both low and high voltages on the same semiconductor substrate. While this xe2x80x9cdual supplyxe2x80x9d approach is simple in circuit implementation, presently, it is substantially more expensive than the traditionally known MOS technology because of the additional processing steps required to fabricate the high-voltage devices. Currently, many 0.2 xcexcm technologies utilize this xe2x80x9cdual supplyxe2x80x9d approach.
Alternatively, several buffer interface architectures are also known in the art for providing high voltage drive capability using low voltage MOS technology. Using this methodology, the incremental costs associated with the additional circuitry required to realize an interface having high voltage drive capability while implemented in low voltage MOS technology are negligible.
Prior approaches to high-voltage drive buffers with low-voltage transistors (HVB/LVT) can be classified into two basic groups. FIG. 1A illustrates a circuit with both high-voltage tolerance and high-voltage drive. Such a circuit is proposed in U.S. Pat. No. 5,663,917 to Oka et al., the entirety of which is hereby incorporated by reference herein. FIG. 1B illustrates a circuit with high-voltage tolerance and low-voltage drive, such as may be found in M. Pelgrom and E. Dijkmans, xe2x80x9cA ⅗V compatible I/O Buffer,xe2x80x9d IEEE J. of Solid-State Circuits, vol. 30, No. 7, p.p. 823-825, July, 1995, the entirety of which is hereby incorporated by reference herein.
For purposes of circuit 10 of FIG. 1A, it is assumed that the breakdown voltage of the transistors used in the circuit is only slightly higher than xc2xd VHIGHxe2x80x94the voltage swing of the input signal. The circuit 10 of FIG. 1A includes a pad driver 12 which includes p-channel and n-channel cascode stacks, which include MOS devices P1, P2 and N1, N2, respectively. The cascode transistors P2 and N2 allow the output at pad node 14 to traverse between 0V and VHIGH while the VGS""s (voltage gate to source) and VGD""s (voltage gate to drain) of all four transistors P1, P2, N1, N2 remain lower than xc2xd VHIGH, and thus lower than the breakdown voltage of the transistors. The voltage capability of the pad driver 12, therefore, is two times larger than the voltage capability of the MOSFETs used in the driver. Such a circuit may be referred to as a xe2x80x9c2xc3x97 driver.xe2x80x9d
For proper operation, the cascode pad driver 12 requires two in-phase input signals at nodes 18 and 20. Both signals must have a voltage swing that does not exceed xc2xd VHIGH in order to avoid exceeding the voltage capability of the transistors used therein. These signals are provided from the level shifter 16 to the driver 12 through two conventional inverter chains. The level shifter 16 takes a 0 to xc2xd VHIGH swing input data signal and produces a data signal that swings between xc2xd VHIGH and VHIGH at node 18. Naturally, the level shifter 16 should be implemented in such a way that none of its transistors experience voltage overstress.
Unlike the circuit 10 of FIG. 1A, the circuit 20 of FIG. 1B is a high voltage buffer with low voltage transistors that is biased from a lower supply voltage xc2xd VHIGH and is characterized by high voltage tolerance but low voltage drive. As a result, its output drive is only between 0 and xc2xd VHIGH. The structure, however, allows the pad voltage to exceed the supply voltage when the buffer is in the tristate mode, i.e., the circuit can be driven by a voltage of approximately VHIGH without damaging the components. The circuit, therefore, may be characterized as having a xe2x80x9c2xc3x97 tolerance.xe2x80x9d The circuit 10 of FIG. 1A may also be characterized as a xe2x80x9c2xc3x97 tolerancexe2x80x9d circuit.
Three problems are eliminated to achieve the 2xc3x97 tolerance of the circuit 20: (a) VDG (voltage drain to gate) overstress of the n-channel transistor N1; (b) conduction of the p-channel transistor P1 in tristate mode when the output node exceeds the supply voltage by approximately a threshold voltage; and (c) forward biasing of the drain-bulk p-n junction of the p-channel transistor P1 when the output sufficiently exceeds the supply voltage. The first problem is resolved by using an n-channel cascodexe2x80x94N2xe2x80x94while the second and the third problems are eliminated by using dynamic gate and bulk biasing (conceptually illustrated using two pairs of switches).
Recently, two HVB/LVT""s with beyond-2xc3x97 voltage capabilities have been reported. A first circuit has a 3.3V drive and 5V tolerance using 2V transistors and is proposed in L. Clark, xe2x80x9cHigh-Voltage Output Buffer Fabricated on a 2V CMOS Technology,xe2x80x9d Digest of Technical Papers, 1999 VLSI Symposium, p.p. 61-62. A circuit that extends the stress free range of a cascode stack beyond the difference between supply and ground by approximately one threshold voltage is proposed in G. Singh and R. Salem, xe2x80x9cHigh-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS Process,xe2x80x9d IEEE J. of Solid-State Circuits, vol. 34, No. 11, p.p. 1512-1525, November 1999. Both circuits use dynamic gate biasing.
While the above referenced circuits address some of the issues involved with interfacing an older higher operating voltage IC with a lower operating voltage technology, the circuits possess significant long term shortcomings. Presently, there is a movement within the semiconductor industry to migrate to sub-0.2 xcexcm sizes towards 0.16 xcexcm, and even 0.13 xcexcm technology powered by sub-1.5V sources. It is expected that within the next four years, the supply voltages may even be in the sub-1V range. As the industry moves below the sub-0.2 xcexcm area and the technologies is powered by sub-1.5V sources, interface buffers will be required to handle greater than the 2xc3x97 multiples of the known art in order to function with older 0.24-0.35 xcexcm powered devices. Thus, the known art is limited as a long term solution due to the migration towards increasingly smaller MOS transistor technologies in view of the continuing commercial viability of older IC components operating at voltages more than twice that of the breakdown voltages of the smaller devices.
As such, there is a need for an improved output buffer capable of interfacing at least two ICs having operating voltages which are multiples equal to or greater than 2xc3x97 and which provides no gate-to-source, gate-to-drain, and drain-to-source stresses while providing at least 2xc3x97 tolerance. Still further, there is a need for a tristate capable high voltage buffer implemented with low voltage transistors that approaches 3xc3x97 voltage capabilities or better.
An integrated circuit includes an output buffer having a maximum voltage that approximates the highest voltage VMAX applicable across at least one pair of nodes of a transistor. The output buffer is capable of delivering an output signal signal having a voltage swing VHIGH of up to about three times the magnitude of VMAX. The output buffer includes at least a first and a second transistor cascode stack, each of the stacks having a driver transistor and at least one cascode transistor. The output buffer also includes a biasing circuit for biasing at least one of the cascode transistors of each of the cascode stacks in response to said output signal such that the magnitude of the voltage applicable across each pair of nodes of each transistor in each cascode stack is less than or equal to VMAX.
The buffer may be utilized to provide a tristate capable buffer circuit with up to 3xc3x97 voltage capabilities, including 3xc3x97 drive and 3xc3x97 tolerance.
The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings.